Testing for stuck-at-faults in CMOS circuits
Asad A. Ismaeel, Z. NAJEM · International Journal of Electronics · 1987
In this paper we utilize an algorithm (Chiang and Vranesic 1983) to test for the classical stuck-at-fault nodes in CMOS transistor level circuits. The original algorithm may incorrectly produce input test patterns. In this paper we suggest a modification to rectify the algorithm. We demonstrate the testing of stuck-at-faults using our modified algorithm in addition to testing of transistors open/short faults. A complete test set for a fault is defined as the set of all input patterns that can detect that fault. Our modified algorithm differs from the original algorithm in that it produces the complete test set for each possible fault. The original algorithm stops searching once it reaches a test set capable of testing all faults. The set which is produced is not guaranteed to be neither complete nor minimal. Finally the paper introduces some programming techniques used in implementing the algorithm