A Hardware Architecture for Elliptic Curve Cryptography and Lossless Data Compression
Miguel Morales‐Sandoval, Claudia Feregrino-Uribe · 2005
We present a hardware architecture that combines elliptic curve cryptography (ECC) and lossless data compression in a single chip. Input data is compressed using a dictionary-based lossless data compressor before encryption, then two elliptic curve cryptographic algorithms can be applied to the compressed data: ECIES for encryption or ECDSA for digital signature. Applying data compression presents three advantages: first, the improvement in the cryptographic module throughput by reducing the amount of data to be encrypted; second, the higher utilization of the available bandwidth if encrypted data is transmitted across a public network and third, the increment of the difficulty of recovering the original information. The architecture was described in VHDL and synthesized for a Xilinx FPGA device. The results achieved show that it is possible to combine these two algorithms in a single chip while gathering the advantages of compression and cryptography. This work is novel in the sense that no such algorithm combination has been reported, nor a hardware implementation of elliptic curve cryptographic schemes.