Reconfigurable VLSI architecture for FFT processor
Tze‐Yun Sung, Hsi‐Chin Hsin, Lu-Ting Ko · WSEAS Transactions on Circuits and Systems archive · 2009
This paper presents a reusable intellectual property (IP) Coordinate Rotation Digital Computer (CORDIC)-based split-radix fast Fourier transform (FFT) core for orthogonal frequency division multiplexer (OFDM) systems, for example, Ultra Wide Band (UWB), Asymmetric Digital Subscriber Line (ADSL), Digital Audio Broadcasting (DAB), Digital Video Broadcasting - Terrestrial (DVB-T), Very High Bitrate DSL (VHDSL), and Worldwide Interoperability for Microwave Access (WiMAX). The high-speed 128/256/512/1024/2048/4096/8192-point FFT processors and programmable FFT processor have been implemented by 0.18µm (1p6m) at 1.8V, in which all the control signals are generated internally. These FFT processors outperform the conventional ones in terms of both power consumption and core area.