Extension of inductive fault analysis to parametric faults in analog circuits with application to test generation
Zbigniew Jaworski, Mariusz Niewczas, W. Kuźmicz · 2002
Parametric fault modeling methodology based on statistical process simulation is proposed. Statistical simulation based on process disturbances allows one to avoid testing for faults which are unlikely to occur. As a result, the number of tests required to verify the circuit's performance is reduced. A practical example with results measured on prototype chips is presented.