A unified signal transition graph model for asynchronous control circuit synthesis
Alex Yakovlev, Luciano Lavagno, Alberto Luigi Sangiovanni-Vincentelli · International Conference on Computer Aided Design · 1992
Characterization of the behavior of an asynchronous system depending on the delay of components and wires is a major task facing designers. Some of these delays are outside the designer's control, and in practice may have to be assumed unbounded. The existing literature offers a number of analysis and specification models, but lacks a unified framework to verify directly if the circuit specification admits a correct implementation under these hypotheses.