Exploring On-Chip Bus Architectures for Multi-Task Applications
Sungchan Kim, Soonhoi Ha · Seoul National University Open Repository (Seoul National University) · 2004
Abstract- In this paper we present a static performance estimation technique of on-chip bus architectures. The proposed technique requires the static scheduling of function blocks of a task to analyze bus conflicts caused by simultaneous accesses from processing elements to which the function blocks are mapped. To apply it to multi-task applications, the concurrent execution of function blocks of different tasks also should be considered. Since tasks are scheduled independently, considering all cases of concurrency in each processing element is impractical. Therefore we make an average estimate on the effect of other tasks with respect to a bus request rate and bus access time. The proposed technique was incorporated with our exploration framework for onchip bus architectures. Its viability and efficiency are validated by a real-life example.