Efficient exploration of the SoC communication architecture design space
Kanishka Lahiri, Anand Raghunathan, Sujit Kumar Dey · 2000
In this paper, we present a methodology and efficient algorithms for the design of high-performance system-on-chip communica-tion architectures. Our methodology automatically and optimally maps the various communications between system components onto a target communication architecture template that can consist of an arbitrary interconnection of shared or dedicated channels. In addition, our techniques simultaneously configure the commu-nication protocols of each channel in the architecture in order to optimize system performance. We motivate the need for systematic exploration of the com-munication architecture design space, and highlight the issues in-volved through illustrative examples. We present a methodology and algorithms that address these issues, including the size and complexity of the design space. We present experimental results on example systems, including a cell forwarding unit of an ATM switch, that demonstrate the benefits of using the proposed tech-niques. Experimental results indicate that our techniques are suc-cessful in achieving significant improvements in system perfor-mance over conventional communication architectures (observed speedups over typical architectures such as single shared buses av-eraged 53%). Moreover, we demonstrate that our design space exploration methodology and optimization algorithms are efficient (low CPU times), underlining their usefulness as part of any sys-tem design flow. I.