Fault simulation of interconnect opens in digital CMOS circuits
H. Konuk · 1997
We describe a highly accurate but efficient fault simulator for interconnect opens, based on characterizing the standard cell library with SPICE; using transistor charge equations for the site of the open; using logic simulation for the rest of the circuit; taking four different factors, that can affect the voltage of an open, into account; and considering the oscillation and sequential behavior potential of opens. A novel test technique based on controlling the die surface voltage is also described. We present simulation results of ISCAS85 layouts using stuck-at and IDDQ test sets. 1 Introduction Breaks are one of the common types of defects that occur during an IC manufacturing process [1]. Breaks fall into different categories depending on their location in a digital CMOS circuit. A break can occur inside a CMOS cell affecting transistor drain and source connections [2, 3, 4, 5]. A break can disconnect a single transistor gate from its driver [6, 7]. Yet another break can disconne...