Efficient architectures for computations over variable dimensional Galois fields
M.A. Hasan, M. Ebtedaei · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 1998
The complexity of many reliability and security schemes, when implemented in hardware, depends on arithmetic operations in the fields over which the computations are performed. In this paper, a multiplier for fields GF(2/sup m/), 1<m/spl les/M, is presented which allows us to vary the field dimension m without changing the hardware. The maximum dimension M that the multiplier can support is determined by the length of the registers and the width of the input arguments of the inner product module used in the multiplier. The proposed multiplier provides bit-serial and pipeline operations. It has a low circuit complexity, and hence it is suitable for applications where area is of prime concern. Using the multiplier, an architecture for multiplication-and-division of polynomials of GF(2/sup m/), 1