Sequential test generation at the register-transfer and logic levels
Abhijit Ghosh, Srinivas Devadas, A. Richard Newton · 1990
The problem of test generation for non-scan sequential VLSI circuits is addressed. A novel method of test generation that efficiently generates test sequences for stuck-at faults in the logic circuit by exploiting register-transfer-level (RTL) design information is presented. Our approach is targeted at chips with data-path like STG.