LOW POWER IMPLEMENTATION OF OPTIMUM COMPOSITE FIELD ARCHITECTURE WITH MINIMAL AREA FOR HIGH-TROUGHPUT AES S-BOXES
V. Usha Reddy G.Supraja, Prasanna Kannan · International journal of advanced research in computer science and electronics engineering · 2013
In this work, we derive novel composite field arithmetic (CFA) Advanced Encryption Standard (AES) S-boxes of the field GF (((2 2 ) 2 ) 2 ). After a sequence of algorithmic and architectural optimization processes a best design is selected. The isomorphic mapping with minimal implementation area and cost functionis chosen for implementation after the exploitation of new common sub expression elimination algorithm.Existing System Performs the 8-bit Galois Field inversion of the S-box using subfields of 4 bits and of 2 bits. This work describes a refinement of this approach that minimizes the circuitry, and hence the chip area, required for the S-box with high speed of operation for applications using larger chips. Through the exploitation we achieved 47.91% area improvement and 11.49% improvement in total power consumption. Normal 0 false false false EN-US X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:Table Normal; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin-top:0in; mso-para-margin-right:0in; mso-para-margin-bottom:10.0pt; mso-para-margin-left:0in; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:Calibri,sans-serif; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Times New Roman; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin;}