An approach for a dynamic generation/validation system for the functional simulation considering timing constraints
Ulrich Heinkel, Wolfram Glauert · 1996
This paper presents a method for the automatic validation of the timing behavior of RT and gate level VHDL descriptions. Using a machine-readable timing specification, we automatically create a VHDL testbench for the stimuli generation and the validation of the expected responses. We have developed a VHDL package using linear programming algorithms to compute a valid set of stimuli. The model responses are checked dynamically subject to the model outputs. A graphical interface is used to specify and validate a timing diagram.. 1. IC design using VHDL Today an ASIC or FPGA designer starts from a verbal, textual or graphical specification to develop a synthesizeable RT level VHDL model. The functional validation of this model is done using a VHDL simulator. Therefore the designer has to create a consistent set of input stimuli. -- VHDL RTL description of a DRAM Entity Modul is Port ( not_RAS IN std_logic not_CAS IN std_logic A IN std_logic_vector 0 to 8 ) not_WE IN std_logic not_OE IN ...