Verification of Asynchronous FIFO using System Verilog
Amit Kumar, Shankar Shankar, Neeraj Kumar Sharma · International Journal of Computer Applications · 2014
As the designs gets complex, the probability of occurrence of bugs increases.This necessitated the introduction of the verification phase for verifying the functionality of the IC and to detect the bugs at an early stage.In this paper, the Asynchronous FIFO design is verified using SystemVerilog.The design uses a grey code counter to address the memory and for the pointer.