8K-point Pipelined FFT/IFFT with Compact Memory for DVB-T using Block Floating-point Scaling Technique
Hui-Gon Kim, Ki-Tae Yoon, Jin-Seon Youn, Jun-Rim Choi · 2009
We Propose a 2K/4K/8K point FFT (Fast Fourier Transform) for OFDM (Orthogonal Frequency Division Multiplexing) of DVB-H (Digital Video Broadcast Terrestrial) Receiver. The proposed FFT architecture utilizes cascaded radix-4 single path feedback (SDF) structure based on the Radix-2/Radix-4 FFT algorithm. We use block floating point scaling technique in order to increase SQNR. The 2K/8K FFT consists of 5 cascaded stages of radix-4 and 3 stages of radix-2 butterfly units. The SQNR of 58 dB is achieved with 10-bit data input, 14-bit internal data and twiddle factors, and 18-bit data output. The core has 75,804 gates with 204,672 bits of RAM and 33,572 bits of ROM using 0.18 um CMOS technology.