On the use of signed digit arithmetic for the new 6-inputs LUT based FPGAs
G.C. Cardarilli, Salvatore Pontarelli, Marco Re, A. Salsano · 2008
In this paper the use of signed digit (SD) arithmetic to better exploit some of the architectural characteristic of the last generation FPGAs is presented. The implementation of Radix-4 SD adders, multipliers and Finite Impulse Response (FIR) filters has been carried out to demonstrate that the use of this number system representation optimally fits the 6-input LUT Logic Elements (LEs) of the newest FPGAs architectures. Comparisons of implementations of the same circuits by using 4-input LUT and 6-input LUT based FPGAs have been carried out showing that Radix-4 SD arithmetic is very efficiently implemented in the last generation FPGAS.