A programmable concurrent video signal processor
Chih-Chin Chen, Chein-Wei Jen · 2002
The video signal processor (VSP) is very suitable for various video standards and provides high flexibility for system development. To offer high throughput and hardware efficiency, we propose a concurrent VSP architecture. Our VSP contains three vector function units that work in parallel. The vector function units adopt a vector-pipeline architecture to increase the throughput and reduce the clock cycle time. To take full advantage of the parallel function units, we design a concurrent control unit which eliminates hazards and schedules instructions. The control unit uses the techniques of reservation stations, renaming buffer, out-of-order execution and in-order completion. With these design considerations, our VSP can encode the full-CIF H.261 video with 30 frames/s at an operation frequency of 47 MHz in the Verilog simulation. We have mapped the design on Xilinx FPGA devices and verified it in a logic analyzer.