A streaming processing unit for a CELL processor
Brian Flachs, Saki Asano, S.H. Dhong, H. Peter Hofstee, Gilles Gervais, R. Kim, T. Le, P. Liu, Jens Leenstra, J. S. Liberty, B. Michael, Hwa-Joon Oh, Silvia Melitta Mueller, Osamu Takahashi, A. Hatakeyama, Yukio Watanabe, Naoka Yano · 2005
The design of a 4-way SIMD streaming data processor emphasizes achievable performance in area and power. Software controls data movement and instruction flow, and improves data bandwidth and pipeline utilization. The micro-architecture minimizes instruction latency and provides fine-grain clock control to reduce power.