WSI implementation of an 8-point FFT
H.A. Nienhaus, David L. Landis · 2002
A parallel architecture for a pipelineable 8-point fast Fourier transform (FFT) which used one-third fewer multiplications than a standard architecture is described. This architecture was developed for wafer-scale integration (WSI) implementation using 2- mu m CMOS and laser restructurable VLSI. Equations for mapping an 8/sup N/-point FFT into a pipeline array of 8-point FFTs are presented.>