A test and maintenance controller for a module containing testable chips
M.A. Breuer, Jung-Cheun Lien · 2003
A design of a module test and maintenance controller (MMC) is presented. Driven by structured test programs, an MMC is able to test every chip in a module via an ETM-BUS or a boundary scan bus. More than one test bus can be controlled by an MMC. MMC processor instructions, when executed, produce bus timing sequences which control a chip's BIT structures. The proposed MMC is a universal design. The difference between MMCs on different modules is the test programs which they executed and the number of test buses they control. Performance analysis indicates that either a RISC (reduced-instruction-set computer)-type processor or DMA controller is required in the MMC. Some self-test features of the MMC are also presented.>