Establishing a lower bound on systolic execution time
Hassan Barada, A. El-Amawy · 2003
A tool called the systolic precedence diagram (SPD), for use in the systematic mapping of compute-bound algorithms into time-optimal systolic architectures, is presented. The SPD graphically displays the computations in accordance with the algorithmic precedence rules under the systolic requirements. It provides a model from which parallel operations are identified and establishes a lower bound on the systolic execution time of an algorithm.>