A 32Gb MLC NAND flash memory with Vth margin-expanding schemes in 26nm CMOS
Tae-yun Kim, Sang-Don Lee, Jin‐Su Park, Ho-youb Cho, Byoung-Sung You, Kwang-Ho Baek, Jaeho Lee, Chang-won Yang, Misun Yun, Minsu Kim, Jong-woo Kim, Eun-seong Jang, Hyun Kyu Chung, Sang-o Lim, Bong-Seok Han, Yo-Hwan Koh · 2011
As the NAND flash memory market grows rapidly due to various applications, such as USB devices, MP3 players, SSDs, cellular phones, and cameras, there is a requirement for high-density and low-cost devices. Two different approaches to meet these requirements are increasing data per cell and area scaling. 3b/cell or 4b/cell NAND flash memories were introduced as an effective way to lower cost. However, these devices suffer from program performance degradation since tighter Vth distribution is required. On the other hand, area scaling is a candidate to achieve low cost while maintaining high program performance even though there are several hurdles to overcome, such as FG coupling and charge retention. As the cell size gets smaller, the Vth distribution widens and the erase-write cycling margin is decreased by the floating-gate coupling ratio.