The intelligent cache controller of a massively parallel processor JUMP-I
Masahiro Goshima, S. Mori, Hiroshi Nakashima, S. Tomita · 2002
This paper describes the intelligent cache controller of JUMP-I, a distributed shared memory type MPP. JUMP-I adopts an off-the-shelf superscalar as the element processor to meet the requirement of peak performance, but such a processor lacks the ability to hide inter-processor communication latency, which may easily become too long on MPPs. Therefore JUMP-I provides an intelligent memory system to remedy the weak point. The cache controller is one of the main components of the memory system, and provides many cache-level supports for inter-processor communication; explicit cache control, high-bandwidth cache prefetching, and a few types of synchronization structures for fine-grained message communication.