Power Supply Noise in Delay Testing
Jing Wang, D.M.H. Walker, Ananta K. Majhi, Bram Kruseman, G. Gronthoud, Luis Elvira Villagra, Paul van de Wiel, S. Eichenberger · 2006
Excessive power supply noise can affect path delay and cause overkill during delay test. This paper presents low-cost noise models for fast power supply noise analysis and timing analysis considering noise impact. Our prior work only considered array-bond chips. This work proposes a noise analysis methodology that can be applied to wire-bond chips as well as array-bond chips. Experiments were performed on an industrial design. Silicon results show as much as a 15% delay variation due to different don't care fill approaches. The power supply noise impact on delay must be taken into account when delay tests are applied