Testing the interconnect of RAM-based FPGAs
M. Renovell, J.M. Portal, Joan Figueras, Y. Zorian · IEEE Design & Test of Computers · 1998
Testing FPGAs before user programming can be an expensive procedure. Applying their general test configuration and test pattern generation methodology, the authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs.