A high precision ramp generator for low cost ADC test
Wen-Ta Lee, Yi-Zhen Liao, Jia-Chang Hsu, Yuh‐Shyan Hwang, Jiann‐Jong Chen · 2008
In this paper, we have proposed a new high precision ramp waveform generator for low cost ADC test. With proposed test method combined with histogram analysis, an ADC can be easily tested on general digital testers. In our approach, we combine a traditional ramp generator with proper gain of operational amplifier (OPA) for ADC test. This new ramp generator structure can reduce the effect of output resistance (Ro) and then get the smaller integral nonlinearity (INL) error. Eventually, we have designed a ramp generator chip using TSMC CMOS 0.35μm 2P4M technology. The core area without I/O pad is 144μmx277μm, operation voltage is 3.3V. Experimental results show that the chip has a ramp signal of 2V full range with duration of 100μS and measured a maximum INL of 20μV only. The linearity of the ramp waveform equals to 16 bits resolution. Such linearity allows the test of ADC up to 14 bits.