Specification and management of timing constraints in behavioral VHDL
F. Curatelli, Leonardo Mangeruca, Marco Chirico · 1996
In this paper a suitable way to specify and manage timing constraints in behavioral VHDL is described. The problem of timing semantics coherency is addressed and a suitable set of procedures is defined to add timing constraint specification in behavioral VHDL for system synthesis. Then, a proper semantics is described which is able to provide a powerful and flexible management of timing constraints.