The high-level generation
Chris B. Edwards · Electronic Systems and Software · 2007
After years in the wilderness, high-level synthesis is moving into chip design with the promise of time savings. In hardware design, most teams today have to describe in fine detail how a logic block will operate. Design using a hardware description language (HDL) is more efficient than the laborious schematic-capture techniques used during the 1980s, but the synthesis tool that uses the HDL as input still has to be told the precise architecture of each block. The designer has to decide whether a multiplier uses carry-save adders and advanced techniques such as Booth recoding or more space- efficient but slower structures. However, the structures that go inside a multiplier are well understood and, in principle, a machine could decide which of a candidate set of multipliers is the right choice. That is the promise of behavioural synthesis - a tool that makes it possible for high-level descriptions of an architecture to generate working logic. Although tools have been around for more than ten years, chip designers are just beginning to take them seriously.