Improving The Testability Of Finite State Machines Implemented By EPLD's
Francesco Corsi, R. Fucci, S. Martino · 1992
It is known that logic redundancies are often present in the implementations of Finite State Machines (FSMS) by regular arrays, owing to both performance reasons und to unoptimized logic. Here we address the problem of designing testable FSMS (i.e. containing the minimum number of redundant faults) implemented by Programmable Logic Devices (PLD). The technique exploits the possible unused input andlor product term lines (p-terms) but does not change the assumed PLD.