Pipeline design tradeoffs in a 32-bit gallium arsenide microprocessor
Veljko M. Milutinović, David A. Fura, W.A. Helbig · IEEE Transactions on Computers · 1991
The results of a study of the instruction pipeline design for a 32-b single-chip GaAs microprocessor are presented. The authors introduce nine candidate solutions for the instruction pipeline, define a set of technology-dependent and application-related parameters, and present the results of the comparative performance evaluation. Important differences between GaAs and silicon, which are relevant for the design of an instruction pipeline, are described. The authors determine the quantitative differences between various candidate solutions. The superb performance of the pipelined memory pipeline in all environments is demonstrated.>