Motion estimation architecture for video compression
Elizabeth Chan, S. Panchanathan · IEEE Transactions on Consumer Electronics · 1993
A VLSI architecture which implements the full search block matching motion estimation algorithm in real time is proposed. The architecture consists of a 2D structure of basic cells (BCs), where each BC is capable of computing the mean absolute error. The interblock dependency is exploited and hence the architecture can meet the real-time requirement in various applications. Most importantly, the architecture is simple, modular, and cascadable. This makes possible VLSI implementation as a codec.>