Coverage Measurement for Software Application Level Verification using Symbolic Trajectory Evaluation Techniques
A. Cheng, Atanas Parashkevov, Cheng‐Chew Lim · 2005
Design verification of a systems-on-a-chip is a bottleneck for hardware design projects. A new solution is a design verification methodology that applies coverage driven verification at the embedded software application level. This methodology currently lacks an appropriate coverage measurement technique. This paper proposes a new coverage model for the software application level. Using this coverage model, a novel technique to represent and measure coverage is described. This technique uses ideas such as control graph structures and checking algorithms to estimate the completeness of software application verification.