A C to hardware/software compiler
Kia Bazargan, Ryan Kastner, Seda Ogrenci-Memik, Majid Sarrafzadeh · 2002
Improvements in FPGA technology have resulted in the introduction of reconfigurable computing machines, where the hardware adapts itself to the running application to gain speedup. We present a top-down compilation method, under development, for such systems. We compile a C program into hierarchical VHDL source files, and annotate them with the placement information of the hardware modules to be configured on the FPGA. Static scheduling combined with a fast, two-stage placement core reduces the compilation time of large programs to minutes.