Timing in systolic systems with variable minimum connection delays
Maximilian Ott, Kazuhiko Enami, M. Hatori, K. Aizawa · 2002
Mapping an originally delay-free dataflow graph onto a systolic hardware consisting of various programmable ALUs (arithmetic logic unit) and a programmable network connecting them will introduce variable extra delays between the processing nodes. To ensure successful mapping it will usually be necessary to increase some of the delays. An algorithm is introduced for calculating these delays and the position to add them. This algorithm was implemented in PicPEn, a programming environment created for the Picot system.>