Design tradeoffs for a 40 MIPS (peak) CMOS 32-bit microprocessor
Derric Lewis, J. Costello, Declan O’Connor · 2003
The RPM40 32-bit CMOS microprocessor system and its initial architectural design tradeoffs are presented. The system is based around two custom VLSI chips, a CPU and an FPU, and has demonstrated programs operating at a 40-MIPS (million-instruction-per-second) peak rate for CPU integer operations. This peak rate is achieved when the CPU pipeline is full, without NOPS, and ignoring cache misses. The peak rate is achieved for many segments of code by careful reorganization of instructions.>