Low peak power ATPG for n-detection test
Sying-Jyan Wang, Kuo-Lin Fu, Katherine Shu-Min Li · 2009
The n-detection test is attractive as it achieves high defect coverage for all types of circuits and different fault models by using an easy ATPG procedure. The drawback is that it requires a much larger test set; besides, the test power is also a concern. Since the size of an n-detection test set is very large, it is possible to organize the test patterns in such a way that signal transitions are distributed more evenly among all patterns; thus, a lower peak capture power can be achieved. The reduction in peak power is very desirable, as it reduces the risk of invalid test due to IR-drop and chip overheating. In this paper, we present a low capture power ATPG and a power-aware test compaction method. Two goals are achieved by the proposed ATPG. (1) The growth of test pattern count is lower than the detection number n. (2) The peak power becomes smaller as the detection number n increases. The test compaction algorithm further reduces the number of test patterns as well as the average capture power. The efficiency of the proposed method is illustrated through experiments with some ISCAS'89 benchmark circuits. Experimental results show that the aforementioned two goals are achieved; furthermore, the average power consumption is also improved when n becomes larger.