A performance study of software and hardware data prefetching schemes
Tien-Fu Chen, J.-L. Baer · 1994
Prefetching, i.e., exploiting the overlap of processor com-putations with data accesses, is one of several approaches for tolerating memory latencies. Prefetching can be ei-ther hardware-based or software-directed or a combination of both. Hardware-based prefetching, requiring some sup-port unit connected to the cache, can dynamically han-dle prefetches at run-time without compiler intervention. Software-directed approaches rely on compiler technology to insert explicit prefetch instructions. Mowry et al.’s soft-ware scheme [13, 14] and our hardware approach [1] are two representative schemes. In this paper, we evaluate approximations to these two schemes in the context of a shared-memory multiprocessor environment. Our qualitative comparisons indicate that both schemes are able to reduce cache misses in the domain of linear array references. When complex data access patterns are considered, the software approach has compile-time in-formation to perform sophisticated prefetching whereas the hardware scheme has the advantage of manipulatingdynamic information. The performance results from an instruction-level simulation of four benchmarks confirm these obser-vations. Our simulations show that the hardware scheme introduces more memory traffic into the network and that the software scheme introduces a non-negligible instruction execution overhead. An approach combining software and hardware schemes is proposed; it shows promise in reducing the memory latency with least overhead. 1