A 28nm 3.6GHz 128 thread SPARC T5 processor and system applications
Venkatram Krishnaswamy, Jinuk Luke Shin, Sebastian Turullols, Jason M. Hart, Georgios K. Konstadinidis, Dawei Huang · 2013
The SPARC T5 processor implements 16 8-threaded SPARC S3 cores, an 8-MB 16-way set-associative L3 cache, 8 BL8 DDR3-1066 schedulers, and integrated PCIe Gen-3. The processor doubles the performance of the previous generation SPARC T4 CPU and expands support for up to 8 socket systems in a single hop glueless fashion. It is implemented in the TSMC 28nm process using 1.5 billion transistors and a 13 layer metal stack. The chip has a maximum operating frequency of 3.6 GHz.