Sequential circuit fault simulation by fault information tracing algorithm: FIT
Yoshihiro Kitamura · 1991
This paper presents a sequential circuit fault simulation method using a Fault Information Tracing algorithm (FIT). FIT handles information which represents how faults on each line propagate to fault convergence gates. By tracing the information backward from primary output, the fault detectability is directly determined. This technique drastically reduces fault effect propagation, achieves precise results, and is applicable to single and multiple stuck-at faults. One of the problems in sequential circuit fault simulation with analytical methods is how to deal with the multiple fault effect which is caused by faults stored in storage elements. Sequential circuit fault simulation by FIT is accomplished by executing multiple fault analysis. The algorithm was implemented in C, and results for ISCAS'89 benchmark circuits are presented.