Imbedded Markov Chains Model of Multiprocessor with Shared Memory
Angel Vassilev Nikolov · 2009
This paper addresses the problem of evaluating the performance of multiprocessor with shared memory and private caches executing Invalidate Coherence Protocols. The model is grounded in queuing network theory and includes bus interference, cache interference, and main memory interference. The method of the Imbedded Markov Chains is used. The highest and lowest performance characteristics are calculated for both equilibrium and transient states. Key words: