VLSI architecture for Rayleigh and Rician fading generators
G. Narasinga Rao, Ratnajit Bhattacharjee, Sukumar Nandi · 2004
In this paper, an architecture suitable for the VLSI implementation of mobile wireless communication channel (Rayleigh and Rician) emulator has been developed and its performance has been evaluated on FPGA platform. The emulator is based on mathematical model proposed by Xiao and Zheng for Rayleigh and Rician fading channels. The proposed design models the mathematical model so as to make it suitable for VLSI implementation. The results obtained from the proposed FPGA implementation have been found satisfactory.