Testing embedded single and multi-port RAMs using BIST and boundary scan
Vladimir Castro Alves, Marcelo Soares Lubaszewski, M. Nicolaidis, Bernard Courtois · 2003
The paper presents a general BIST scheme for the test of RAMs (single and multi-port) embedded in very complex ASICs. A simple BIST circuit driven by the IEEE standard for the boundary scan (BS) is shared by all the memories that are tested simultaneously. The area overhead is greatly compensated by the test development time reduction and the link with BS.>