New challenges in delay testing of nanometer, multigigahertz designs
Terrence Mak, A. Krstić, Kwang-Ting Tim Cheng, Li-C. Wang · IEEE Design & Test of Computers · 2004
Less predictable path delays and many paths with delays close to the clock period are the main trends affecting the delay testability of deep-submicron designs. We examine the challenges in meeting the quality requirements of gigascale integration, and explore functional testing as well as statistical models and methods that could alleviate some of those problems.