CMOS PA-RISC processor for a new family of workstations
M. Forsyth, S. Mangelsdorf, E. DeLano, Craig Gleason, J. Yetter, D. Steiss · 2002
A novel low-cost, high-performance RISC (reduced instruction set computer) processor chip set implementing Hewlett Packard's PA-RISC instruction set has been developed. The design consists of a CPU chip containing 577 K transistors implemented in HP's CMOS26 technology and a floating-point coprocessor containing 640 K transistors and implemented in Texas Instruments' EPIC-2 CMOS technology. Key features of the design include a 66 MHz clock frequency, large configurable cache memories utilizing industry standard SRAMs, and several implementation features designed to improve floating-point and graphics performance.>