Configurable high-throughput decoder architecture for quasi-cyclic LDPC codes
Christoph Studer, Nicholas Preyss, Christoph Röth, Andreas Peter Burg · 2008
We describe a fully reconfigurable low-density parity check (LDPC) decoder for quasi-cyclic (QC) codes. The proposed hardware architecture is able to decode virtually any QC-LDPC code that fits into the allocated memories while achieving high decoding throughput. Our VLSI implementation has been optimized for the IEEE 802.11 n standard and achieves a throughput of 780 Mbit/s with a core area of 3.39 mm2in 0.18 mum CMOS technology.