Architecture and design of a second-level cache chip with copy-back and 160 MB/s burst-transfer features
Kota Uchiyama, Hirokazu Aoki, Osamu Nishii, S. Hatano, O. Nagashima, K. Ooishi, J. Kitano · 1990
The authors describe the architecture and design of a second-level cache chip which supports high-speed (160-Mb/s) burst transfer between multilevel caches and a newly proposed cache-consistency protocol. This chip includes a 32-kB data memory as well as a 42-kb tag memory and 21.7 K-gate logic, and it supports a 50-MHz CPU. Performance and design results are presented