Throughput optimized architectural synthesis
Catherine H. Gebotys · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1993
This paper presents for the first time an optimization approach to synthesizing DSP-specific architectures which maximize throughput. A new integer programming (IP) model is presented that supports simultaneous scheduling, allocation, and retiming or loop winding. The IP model is used to map a DSP application to a high speed application-specific architecture which maximizes throughput given constraints on area and latency. Results show this approach optimally synthesizes architectures that have up to 12% higher throughputs than previously published architectures. This research provides industry with a DA tool for mapping DSP applications to high performance architectures optimized for throughput.>