Dynamic Barrier Architecture For Multi-Mode Fine-Grain Parallelism Using Conventional Processors Part I: Barrier Architecture
William E. Cohen, Hank G. Dietz, J. B. Sponaugle · Purdue e-Pubs (Purdue University System) · 1994
Parallel computers constructed using conventional processors offer the potential to achieve large improvements in execution speed at reasonable cost, however, these machines tend to effi-ciently implement only coarse-grain MIMD parallelism. To achieve the best possible speedup through parallel execution, a computer must be capable of effectively using all the different types of parallelism that exist in each program. Acombination of SIMD, VLIW, and MIMD paral-lelism, at a variety of granularity levels, exists in most applications; thus, hardware that can sup-port multiple types of parallelism can achieve better performance with a wider range of codes. In this paper, weintroduce a new hardware barrier architecture that provides the full DBM functionality we discussed in [OKD90a], but can be implemented with much simpler hardware. This mechanism can be used to efficiently support multi-mode moderate-width parallelism with instruction-level granularity (i.e., synchronization cost is approximately one LOAD instruction), as described in the companion paper [CoD94].