QC-LDPC Decoding Architecture based on Stride Scheduling
Bongjin Kim, In‐Cheol Park · 2011
In this paper, an area-efficient decoder architecture is proposed for the quasi-cyclic low-density parity check (QC-LDPC) codes specified in the WiMAX 802.16e standard. In order to achieve low area and maximize hardware utilization, the decoder utilizes 4 decoding function units, which is the greatest common divisor of the expansion factors. Furthermore, the decoder adopts a novel scheduling scheme, named as stride scheduling, to remove the conventional flexible permutation network and also minimize the number of memory accesses. The synthesized decoder costs 49K of logic gates and 54,144 bits of memory, while maintaining the throughput over the requirement of the WiMAX.