An 800-MHz quadrature digital synthesizer with ECL-compatible output drivers in 0.8 μm CMOS
Loke Kun Tan, E.W. Roth, G. Yee, Henry Samueli · IEEE Journal of Solid-State Circuits · 1995
An 800 MHz quadrature direct digital frequency synthesizer (QDDFS4) chip is presented. The chip synthesizes 12 b sine and cosine waveforms with a spectral purity of -84.3 dBc, The frequency resolution is 0.188 Hz with a corresponding switching speed of 5 ns and a tuning latency of 47 clock cycles. The chip is also capable of frequency and phase modulation. ECL-compatible output drivers are provided to facilitate I/O compatibility with other high speed devices. A high gain amplifier at the clock input enables the QDDFS4 chip to be clocked with ac-coupled RF signal sources with peak-to-peak voltage swings as small as 0.5 V. The 0.8 /spl mu/m triple level metal N well CMOS chip has a complexity of 94000 transistors with a core area of 5.9/spl times/6.7 mm/sup 2/. Power dissipation is 3 W at 800 MHz and 5 V.