High performance stereo computation architecture
Javier Díaz, Eduardo Ros, Sonia Mota, Eva M. Ortigosa, Begoña del Pino · 2005
A simple and fast technique for depth estimation, based on phase measurement has been adopted for the implementation of a real-time stereo system with subpixel resolution on a FPGA device. The technique avoids the attendant problem of phase warping. The designed system takes full advantage of the inherent processing parallelism of FPGA devices to achieve a computation speed of 65 Megapixels per second that can be arranged with a customized frame grabber module to process 52 frames per second of 1280 /spl times/ 960 pixel resolution. The achieved processing speed is higher than existing approaches. This allows the system to extract real-time disparity values for very high resolution images or use several cameras to improve the system accuracy.